Conventional volatile memory cells, such as dynamic random access memory (DRAM) cells, may include a capacitor and a transistor. The capacitor may be referred to in the art as a cell capacitor or a storage capacitor. The transistor may be referred to in the art as an access transistor. The transistor conventionally includes a channel region between a pair of source/drain regions and a gate configured to electrically connect the source/drain regions to one another through the channel region. The channel region is usually formed of a semiconductor material.
The transistor functions to apply or remove charge on the capacitor, thus affecting a logical state, e.g., a binary value of either 0 or 1, defined by the storage charge. The binary value of a cell is generally determined by “reading” the cell. Reading the cell involves sensing the voltage stored by the capacitor and comparing that voltage to a reference voltage. If the detected stored voltage meets or exceeds the reference voltage, the cell may be read at a logical state of 1; otherwise, the cell may be read at a logical state of 0. After reading, the access transistor may be further used to re-charge the capacitor to return the capacitor to a charge corresponding to the read logical value.
To charge, discharge, read, or recharge the capacitor, the transistor may be selectively turned to an “on” state, in which current flows between the source and drain regions through the channel region of the transistor. The transistor may be selectively turned to an “off” state, in which the flow of current is substantially halted. Ideally, in the off state, the capacitor would retain, without change, its charge. However, capacitors of conventional volatile memory cells experience discharges of current over time. Therefore, even in the “off” state, a conventional volatile memory cell will often still undergo some flow of current from the capacitor. This off-state leakage current is known in the industry as a sub-threshold leakage current.
To account for the sub-threshold leakage current and to maintain the capacitor of the memory cell at an appropriate charge to correspond to its intended logical value, conventional volatile memory cells are frequently refreshed. Refreshing may involve reading the logical value of the cell, which reading may decrease the charge of the capacitor, and then, if necessary, recharging the capacitor to return the cell to the read logical value. A conventional DRAM memory cell may, for example, be refreshed as frequently as every 64 microseconds. The appropriate refresh frequency, which is determined by the rate of current leakage through the channel, impacts at what voltage the capacitor must be charged to correspond to the appropriate logical value. For example, when the sub-threshold leakage current is relatively high, the capacitor must generally be charged to a relatively high voltage so that an accurate logical value will be detected at the appropriate time. Otherwise, supplying the capacitor with too low of a charge could lead to a mis-read in the cell's logical value after a period of time.
Refreshing DRAM memory cells consumes a certain amount of power. Where an array of memory cells of a memory device is incorporated within a portable device, for example a so-called “smart” phone such as an IPHONE® or a BLACKBERRY® device, the power consumed by the memory device to refresh the cells and account for sub-threshold leakage current affects the length of time during which the portable device may be used before batteries must be recharged or the device must be connected to an external power supply.
The sub-threshold leakage current can also impact the fabrication and configuration of an array of memory cells within a memory device. Fabricating a semiconductor memory device upon a substrate necessarily leads to occupation of a certain surface area of the substrate by the footprint of the cell within the device. Memory cells are often constructed in arrays, in which individual cells are arranged in columns and rows, upon the primary surface of the substrate. The primary surface is generally the uppermost, exterior surface of the substrate. Often, the available area on a given substrate's primary surface is limited, and maximizing the use of the substrate requires maximizing the density of devices fabricated on the substrate and therefore also the density of cells fabricated within each device. In a planar array of semiconductor cells occupying the same horizontal plane, such as the surface of the substrate, maximizing cell density includes not only minimizing the size of the cells but packing the cells as close to one another as possible without damaging the operability of the cells. If volatile memory cells are packed too closely to one another, unwanted current leakage paths may inhibit the operation of the cell. These unwanted current leakage paths may be through the channel region of the transistor or through other components of the cell, such as the dielectric material of the capacitor.
Efforts have been made to increase cell density by fabricating semiconductor cells, including memory cells, in three-dimensional arrays, also known as stacked arrays. However, when fabricating stacked arrays of cells, thermal budgets set by the components of already-fabricated components in the stack are a consideration when additional components are added. That is, fabrication of components of a memory cell often involves heating materials of already-fabricated components of the cell to temperatures well in excess of 200 degrees Celsius. After fabricating a first array of semiconductor components, when fabricating a second array of components stacked above the first array, it is desirable not to use fabrication processes that require processing temperatures high enough to potentially damage the already-formed components in the first array.
Accordingly, sub-threshold leakage current rates, refresh rates, cell size, and thermal budgets of memory cells are often important considerations in the design, fabrication, and use of volatile memory cells and arrays of cells incorporated in memory devices.